A random access memory (RAM) device includes a memory array with numerous memory cells interconnected to store information. Non-volatile memory (“NVM”) cell, such as Silicon-Oxide-Nitride-Oxide-Silicon (“SONOS”) type of NVM cell, is distinguished from mainstream flash by the use of silicon nitride instead of polysilicon for the charge storage material.
SONOS cells are generally formed from a standard polysilicon N-channel MOSFET transistor with the presence of a small sliver of silicon nitride inserted inside the transistor's gate oxide. The sliver of nitride is non-conductive but contains a large number of charge trapping sites able to hold electrostatic charge. The nitride layer is electrically isolated from the surrounding transistor, although charges stored on the nitride directly affect the conductivity of the underlying transistor channel.
When the polysilicon control gate is biased positively, electrons from the transistor source and drain regions will tunnel through the oxide layer and get trapped in the silicon nitride. This results in an energy barrier between the drain and the source, thereby raising the threshold voltage. The electrons can be removed and the cell erased by applying a negative bias on the control gate. A select gate may be used to eliminate over-erase cell disturb issues, however, this will result in larger feature size as 2 transistors are needed for every single memory cell built. This will result in the need for a larger chip area in order to accommodate the components, which would in turn results in higher costs. Additionally, it is also desirable to achieve other benefits e.g., high mobility and low random dopant fluctuation (“RDF”), etc.
From the foregoing discussion, it is desirable to provide improved and compact NVM memory cells. It is also desirable to provide a simplified method for forming such NVM memory cells.